Testing of an IC is a critical part of circuit development. Factors that affect IC testing include the number of components to be tested in the circuit, the ability to access lines or nodes that carry signals indicating the condition of the components, and the fact that the number of IC pins is normally quite small compared to the number of IC components. As ICs become increasingly more complex, IC testing poses increasing challenges.
Inherent to the development of many ICs is the concept that an IC should be designed in such a manner as to facilitate its testing. This is commonly referred to as design for testability. Two attributes of testability are controllability and observability. Controllability refers to the ability to establish a desired signal value at an internal circuit node by setting appropriate values at the circuit's inputs. Observability refers to the ability to determine the signal value at an internal node by controlling the circuit's input signals and observing the circuit's output signals.
In designing an IC to be testable, keeping the pin count low is typically an important consideration. In other words, the number of pins dedicated to testing the IC should be small. One way of enhancing controllability and observability without paying a large price in test pins is to incorporate a scan register in the IC. A scan register is a group of one-bit registers which can be loaded in parallel and through which information can be shifted from register to register. See Abramovici et al, Digital Systems Testing and Testable Design (Computer Science Press), 1990, pages 358-412.
The Joint Test Action Group ("JTAG") boundary-scan approach governed by the IEEE 1149.1 Testability Bus Standard is an example of the scan-register technique. In the boundary-scan standard, boundary-scan cells are situated along the periphery of an IC between the IC's functional (or application) circuitry and the IC's functional input/output ("I/O") pins. In particular, each boundary-scan cell is located between a functional I/O pin and part of the functional circuitry. Each cell typically contains a pair of one-bit registers and multiplexing circuitry for controlling data movement. During normal circuit operation, the multiplexing circuitry enables data to pass through the boundary-scan cells without being affected by the cells. Accordingly, the boundary-scan cells are transparent to the functional circuitry during normal IC operation.
The boundary-scan cells are connected in a chain so that test data can be synchronously shifted--i.e., moved in synchronism with pulses of a clock signal--from one cell to the next in the chain. The cell at one end of the chain is connected to a test input pin through which data is synchronously shifted into the scan cells. Data is synchronously shifted out of the scan cells through a test output pin connected to the cell at the other end of the chain. During test operation, data for testing the functional circuitry can be loaded into the scan cells in parallel from the functional I/O pins or by shifting data in through the test input pin. Test results are determined by observing the functional I/O pins or by observing the test output pin as data is shifted out of the IC.
The boundary-scan approach is useful in testing the general operational characteristics of sequential logic circuitry--i.e., circuit portions having state elements that change value in synchronism with clock pulses. However, the boundary-scan technique provides little capability to test asynchronous logic in which changes in signal value depend on transmission delays through the circuit.
In fact, testing asynchronous digital circuitry is particularly difficult. Unlike synchronous digital circuitry in which signals at internal nodes are set at values long enough to be clocked into state elements so as to be observable, signal values at internal nodes in asynchronous digital circuitry sometimes make multiple changes in value between consecutive pulses of a clock otherwise adequate for testing synchronous circuitry. Such changes in signal value in asynchronous circuitry thus cannot be entered into state elements to be observed.
Furthermore, signal transmission delay is an important parameter in asynchronous digital circuitry. Techniques, such as boundary scan, which are useful in testing synchronous circuitry typically furnish, at best, only a crude approximation of transmission delay. In many ICs, little testing is done on internal asynchronous circuitry. Accordingly, it would be highly advantageous to have a pin-efficient technique for testing asynchronous digital circuitry.